As CMOS technology continues to scale, integrated circuit designs are increasingly affected by the variability in the back end of the line. In order to achieve acceptable design quality, theses variations should be well understood so that their impact can be taken into account in circuit and layout design flow.
Chemical Mechanical Planarization (“CMP”) is a primary technique to planarize layout surfaces in order to establish reliable multilevel copper interconnects, and constitutes one or more steps in a typical semiconductor manufacturing process. In modern manufacturing processes, after depositing a new layer of material on previous layers of material along with an insulating dielectric, a chemical mechanical polishing step removes excess materials and planarizes a target surface with a combination of chemicals and mechanical forces. The smooth surface is nessary to maintain photolithographic depth of focus for subsequent steps and also to ensure establishing reliable multilevel copper interconnects.
However, due to dishing and erosion, thickness variations still exist after a CMP process. Intra-chip copper interconnect variation can be on the order of 20-40%. In order to capture thickness variations after a CMP process, a number of CMP simulators have been proposed, and several EDA vendors have developed industrial tools (comprehensive simulation tools) to simulate CMP processes.
As feature sizes drop below 90 nm, boundaries between design and manufacturing become blurred, and Design for Manufacturability (“DFM”) has been established as an important concept in nanometer circuit design. It is highly desired to incorporate the effects of CMP processes in layout and design so that the CMP-induced copper thickness variations, which may affect wire resistance and capacitance, and further lead to timing changes, can be accurately captured during the design stage. In the “2D”, RC extractors have to set a large conservative full chip guard band (around ±20%) in order to cover both systematic and random thickness variations in copper interconnects.
It is known that full chip CMP modeling can accurately predict systematic variations in metal layers and help to eliminate the systematic variation guard band leaving only a relatively small random variation guard band. This helps to reduce the pessimism on timing estimation and increase the overall net delay accuracy. References shows that when comparing the worst case analysis, the total capacitance with CMP-aware timing is smaller by up to 12% of the capacitance when compared to the traditional approach. The traditional approach does not consider CMP effects. Also the delay of 93% of the critical path is decreased when the CMP effects are considered during timing. Therefore, CMP simulation can help to improve timing analysis and make aggressive design possible. However, although several accurate CMP models exist, there are still significant challenges in applying these models to the design stage due to the following three reasons.
First, modeling must reflect the effect of dummy fills. In order to get accurate CMP predictions, a proposed model requires a full design that includes not only every component in the design, but also dummy fills. However, in large-scale integrated circuit designs, the hierarchical approach is widely adopted such that designers may work only on part of the design, and no full chip information is available. Furthermore, dummy fills are required by almost all foundries for local metal density adjustment. (Some foundries also have requirements on cheesing holes). Fills and holes are usually inserted in the product layout post design stage, and the fills (holes) have a large impact on layout smoothness. Simulation results show that standard deviations on copper interconnect thickness variations can change by 58% as a result of incorporation of dummy fills. In short, a full design with fills and holes is required for accurate CMP prediction.
Second, the execution time of a full chip CMP prediction is long, measured by hours. However, the design process is an iterative process, and multiple iterations are required to refine and optimize the design. This means that the CMP copper interconnect model may be called multiple times. So the run time of the CMP model has to be short enough to facilitate a tight and timely design schedule. A long execution time for a CMP model can greatly restrict its application in the design stage.
At the late design stage, incremental optimizations are highly desired in order to honor existing designs while improving the performance and tackling design changes. In general, these incremental operations are applied only in small, localized regions of a design, and the majority of the design stays unchanged. Ideally, CMP predictions should be updated for only those changed regions. However, the CMP models have to consider the long range impacts, and will still take the full chip information for a full chip prediction, which takes a long time to complete.
Accordingly, those skilled in the art seek methods, apparatus and computer program products that overcome these limitations of the prior art.